Xilinx gains exclusive rights to 3G turbocoder

date: 24th January 2001, source: eetimes.com

Frontier Design NV has designed a turbocoder circuit for forward error correction in third-generation (3G) wideband-CDMA mobile basestations and handsets, starting from algorithms expressed in the C programming language.

The company, which supports DSP-based design with EDA tools and algorithmic development, has also optimized the core for implementation as transferrable intellectual property (IP) for use in Xilinx's Virtex-II field-programmable gate arrays (FPGAs).

Frontier (Leuven, Belgium) said that under an agreement with Xilinx, the turbocoder in this form would be marketed and sold exclusively by Xilinx, while Frontier would retain ownership of the C language algorithms and seek to win design service contracts for ASIC implementations of the turbocoder core. Frontier is also offering customization services to Xilinx customers.

Forward error correction based on turbocoding principles is a key piece of intellectual property for the 3G WCDMA air interface, which looks set to be dominant in Europe, Japan and Korea. It is being standardized by the Third Generation Partnership Program (3GPP).

The 3GPP standard requires turbocoding block lengths of between 40 and 5,114 bits with 2-Mbit/second data throughput, a bit error rate of 1 bit per million, a 3-decibel signal-to-noise ratio and the capability to perform multiple iterations.

Two tacks

One of two algorithmic approaches can be used for data encoding and decoding: the Log Max* or the Max Log algorithm. Frontier has created a highly parallelized turbocoder IP core for Xilinx FPGAs that it claims can execute the more accurate Log Max* algorithm and still reach the 2-Mbit/s throughput required by the 3GPP standard.

As a result, Frontier states, when the Xilinx turbocoder is included in a 3GPP WCDMA system, the signal-to-noise ratio is at least 0.5 dB greater than that of designs based on other turbocoder cores.

Turbocoders perform error correction by comparing two versions of an encoded data stream and computing the probability that the two data streams are the same.

Feeding the results of the comparison back into the Maximum Aposteriori decoder increases the accuracy of the error correction. The more decoding iterations that are performed, the more accurate the error correction.

Along with touting superior accuracy and the ability to support more channels as key features of its new design, Frontier claims its use of "windowing" memory technique has reduced the total double-buffered memory requirement from 41 kbytes — not available on any FPGA — to 8 kbytes. That means a single-chip solution based on an XCV400E FPGA is possible.

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