Motorola Selects Agilent Technologies' Automated Test System for New 3G Wireless Communications SOC Device

date: January 28, 2002

Agilent Technologies today announced that Motorola's Semiconductor Products Sector (SPS) has chosen the Agilent 93000 SOC Series test system as the platform to test a new baseband processor for third-generation (3G) wireless communications. Motorola's choice was based on the 93000's ability to reduce overall test time by more than 50 percent.

"The Agilent 93000 SOC Series significantly reduced our per-device test time, driving down our cost of test and helping us come out ahead in this highly competitive consumer electronics market," said Errol Moore, corporate vice president and director at Motorola, SPS. "The system's at-speed memory test performance also convinced us that the 93000 was the best choice for our complex embedded memory products."

Testing embedded memory on an SOC is a complex, time-consuming process. Reducing memory test time is therefore a key factor in reducing overall SOC test time and cost of test. The Agilent 93000 SOC Series' test processor-per-pin architecture allows at-speed memory testing, enabling the system to test DRAM and SRAM at higher frequencies, improving test coverage and reducing memory test times by as much as 75%. In addition, at-speed testing allows scan and ATPG patterns to be tested at higher speeds, improving test coverage and further reducing test times.

Motorola is using the Agilent 93000 SOC Series Ce model to test their new baseband processor. The Agilent 93000 Ce model offers a low price point yet provides the architecture to cover a broad range of SOC applications. In addition, the tester's port scalability allows the end user to configure performance on a pin-by-pin basis. The result is a versatile tester that is less expensive not only to buy, but also to own.

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