Altera Offers Optimized Correlator IP Architecture for CDMA and WCDMA

date: September 28, 2001

Available immediately today from Altera Corporation is its correlator megafunction and Direct Sequence Spread Spectrum (DSSS) reference design. Both specifically optimized for the CDMA and W-CDMA standards, this joint offering of intellectual property and a corresponding reference design allows engineers to simplify the design of wireless basestations and baseband modems, significantly reducing the time from concept to hardware implementation.

Both the correlator and the DSSS reference design can be used with the DSP development kit for APEX devices for easy prototyping and debugging of designs for the next generation of wireless basestations. Accompanying the DSP development kit for APEX devices, Altera's DSSS reference design illustrates the use of the Altera's correlator megafunction, FIR compiler and NCO compiler for various channelization and spreading/dispreading techniques. In addition, the 3GPP has recently adopted DSSS as the channelization technique for 3G W-CDMA basestations.

One of the fundamental building blocks of wireless basestations, the correlator function is primarily used for spreading/despreading, random access channel (RACH) detection, and synchronization of data in baseband modem section of the wireless basestation. By optimizing the correlator and its corresponding reference design, Altera delivers significant cost savings by reducing the logic area compared with competing architectures. For example, using Altera's new patented architecture, a RACH detector consumes only 5,000 logic elements (LEs) in an APEX II device, which is at least 50 percent more efficient than competing solutions.

Systems designers can easily create custom functions with the interactive MegaWizard Plug-In Manager for the correlator MegaCore function. Using the MegaWizard Plug-In Manager, the designer can easily change system parameters such as block length, number of chips, and oversampling.

The correlator MegaCore function is one of the many IP cores that have an Avalon bus interface for microprocessor control using Altera's Excalibur embedded processor solutions -- the industry's only embedded processor based programmable logic device (PLD) family. Combining logic, memory, and a processor core, Altera's Excalibur embedded processor solutions provide engineers with the flexibility of integrating a complete system-on-a-programmable-chip (SOPC) solution.

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